Analytical and design techniques for drag reduction studies on wavy surfaces

Numerical models for two dimensional turbulent boundary layers over wavy surfaces were investigated. Computations for wavy wall boundary layers indicate possibilities of overall drag reduction in a parameter range of the geometry of the wall. The correction technique using integral methods for analyzing arbitrary surfaces was found to be unsuitable for some cases of interest in drag reduction; a Navier-Stokes solver for wavy walls was built to test these problems. Test results of the Navier-Stokes solver indicate that the solution techniques are accurate enough to handle complex geometries and steep variations in fluid properties

A general algorithm using finite element method for aerodynamic configurations at low speeds

A finite element algorithm for numerical simulation of two-dimensional, incompressible, viscous flows was developed. The Navier-Stokes equations are suitably modelled to facilitate direct solution for the essential flow parameters. A leap-frog time differencing and Galerkin minimization of these model equations yields the finite element algorithm. The finite elements are triangular with bicubic shape functions approximating the solution space. The finite element matrices are unsymmetrically banded to facilitate savings in storage. An unsymmetric L-U decomposition is performed on the finite element matrices to obtain the solution for the boundary value problem

Upper Bounds for the Davenport Constant

We prove that for all but a certain number of abelian groups of order n its Davenport constant is atmost n/k+k-1 for k=1,2,..,7. For groups of order three we improve on the existing bound involving the Alon-Dubiner constant.Comment: article soumis, decembre 200

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared

Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits

In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used extensively in nanoelectronic digital circuit synthesis. The mathematical formulae derived to evaluate the logical masking capability of majority gates holds well for minority gates, and a comparison with the logical masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR is provided. It is inferred from this research work that the logical masking capability of majority/minority gates is similar to that of XOR/XNOR gates, and with an increase of fan-in the logical masking capability of majority/minority gates also increases